Each CPU has its own cache and coordination is needed. This applies not only to CPUs but also in a distributed sense (redis, memcached).
Coherency
- Values in all caches are consistent
- The system behaves as if all CPUs are using shared memory
Action is either:
- Update
- Invalidate
Invalidate
This is the most common technique and notes that data is out of date.
States
MSI and MESI:
- Modified: Only this cache has a valid copy and main memory is out of date
- This value has been modified and is dirty
- We need to write-back before sharing (set state to shared)
- Exclusive: Only this cache has a valid copy and main memory is up to date
- Can silently upgrade to M on write
- Shared: Location is unmodified and is up to date with main memory
- Data is clean
- Reads allowed but we need to coordinate writes now
- Invalid: Cache is out of date
- Must get memory from another cache
There is also MESIF which has a forward state which is a shared state except, the current cache is the only one that will respond to a request to transfer the data. The reason you would do this is to permit more effective use of the bus since a processor requesting data that is already shared will get once response transferring the data.
False sharing
When a program has two unrelated data elements that are mapped to the same cache line